1. Field of the Invention
The present invention is directed in general to integrated circuit memories. In one aspect, the present invention relates to a static random access memory.
2. Description of the Related Art
Static random access memories (SRAMs) are generally used in applications requiring high speed, such as microprocessors and other data processing systems which use register files and memories for high speed computing. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters which are stable in one of two possible voltage levels, and the logic state of the cell is determined with a pair of access transistors, thereby creating the basic six-transistor (6T) SRAM architecture. The read stability and writability of SRAM cells have been improved by adding additional transistors to the basic 6T architecture. For example, 8T and 10T subthreshold SRAMs have been proposed which provide single-ended read sensing, but such single-ended read sensing methods still suffer from bitline noise resulting from transients, process variations, soft error, and power supply fluctuations which may cause the cell to inadvertently change logic states. To achieve a larger static noise margin (SNM), the dimensions of the memory cell should be enlarged, but this results in reduced output speed. Accordingly, a need exists for improved SRAM cell design to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.